1. Field of the Invention
Embodiments of the invention relate to semiconductor devices that can be used in a half-bridge power source and have a level shift circuit.
2. Related Art
The circuit of a half-bridge power source or the like is typically configured as shown in FIG. 15. This circuit is provided with an output circuit 60 in which a high-potential-side switching element XD1 and a low-potential-side switching element XD2 are connected in series. An input buffer and protection circuit 70 that generates a high-side drive signal Hdrv for driving the high-potential-side switching element XD1 and a low-side drive signal Ldrv for driving the low-potential-side switching element XD2 is connected to the output circuit 60. This circuit is also provided with a low-side drive circuit 80 that outputs a drive signal LO for driving the low-potential-side switching element XD2 on the basis of the low-side drive signal Ldrv. This circuit also includes a high-side drive circuit 90 that transmits the high-side drive signal Hdrv, which is a pulse signal of a low-potential system outputted from the input buffer and protection circuit 70, to the high-potential system and drives the high-potential-side switching element XD1.
The present invention relates to a high-side drive circuit and uses the conventional technique for the low-side drive circuit. Therefore, the explanation of the low-side drive circuit is hereinbelow omitted.
The configuration of the high-side drive circuit 90 is explained below with reference to FIG. 16. The high-side drive circuit 90 is provided with a pulse generating circuit 91, two level shift circuits 93, 94, a latch malfunction protection circuit 95, a latch circuit 96, and a high-side driver 97.
The pulse generating circuit 91 outputs two micro-pulse signals synchronized with the rise edge and fall edge of the high-side drive signal Hdrv, which is a pulse signal of a low-potential system outputted from the input buffer and protection circuit 70. The micro-pulse signal synchronized with the rise edge of the high-side drive signal Hdrv is a set signal (SET) for setting ON the high-potential-side switching element XD1. The micro-pulse signal synchronized with the fall edge of the high-side drive signal Hdrv is a reset signal (RESET) for setting OFF the high-potential-side switching element XD1.
The level shift circuit 93 shifts the level of the set signal (SET) outputted from the pulse generating circuit 91 to a high-potential system and outputs a level-shifted set signal (SETDRN), which is the set signal of the high-potential system. The level shift circuit 94 shifts the level of the reset signal (RESET) outputted from the pulse generating circuit 91 to a high-potential system and outputs a level-shifted reset signal (RESDRN), which is the reset signal of the high-potential system.
The latch circuit 96 latches the level-shifted set signal (SETDRN) and the level-shifted reset signal (RESDRN) and outputs the latched signals. The high-side driver 97 outputs a drive signal HO that drives the high-potential side switching element XD1 on the basis of the signals latched by the latch circuit 96. The latch malfunction protection circuit 95 is provided at the front stage of the latch circuit 96 and prevents the latch circuit 96 from malfunctioning.
FIG. 17 is an operation time chart of the conventional high-side drive circuit 90. The set signal (SET) is outputted at the fall of the control input signal Hdrv, and the reset signal (RESET) is outputted at the rise of the Hdrv. The level-shifted set signal (SETDRN) and the level-shifted reset signal (RESDRN), which are the outputs of the level shift circuits 93, 94, are outputted as respective negative logic signals. In a control signal output circuit 92 constituted by the latch malfunction protection circuit 95, latch circuit 96, and high-side driver 97, on the basis of those signals, the drive signal H0 is ON when the SETDRN signal is negative (effective), and the drive signal H0 is OFF when the RESDRN signal is negative (ineffective). When the drive signal H0 is ON, the high-potential-side switching element XD1 is in a conductive state, and when the drive signal H0 is OFF, the high-potential-side switching element XD1 is in a non-conductive state.
Where the switching elements XD1, XD2 are driven and electric power is supplied to an inductive load L1, the electric potential Vs of a contact point P1 of the switching elements can change, thereby generating dV/dt noise.
A technique has been suggested for preventing the malfunction caused by the dV/dt noise, which is the noise generated by abrupt voltage changes (dV/dt) caused by the operation of the switching elements.
For example, Japanese Patent Application Publication No. 2011-139423 (also referred to herein as “Patent Document 1”) suggests a technique that can prevent the malfunction caused by dV/dt noise, without generating a through electric current, by the feedback of the output of a latch circuit to a level shift circuit side.
Japanese Patent No. 3773863 (also referred to herein as “Patent Document 2”) suggests a technique for preventing the malfunction by applying a continuous pulse (repetitive pulse) to each of two level shift circuits.
However, the techniques described in the aforementioned Patent Document 1 and Patent Document 2 each use two level shift circuits, one on the set side and one on the reset side, an out-of-synch operation caused by a spread in characteristics of device elements on the set side and reset side inside a semiconductor device appears when an abrupt voltage change (dV/dt) occurs due to the operation of switching elements, and this out-of-synch operation causes a malfunction. For example, a spread in parasitic capacitances Cds1, Cds2 can be the aforementioned spread in characteristics of device elements.